Conventional asynchronous memory circuits are triggered internally by an address transition detection to initiate read and write accesses. The address transition detection produces a self timing event that cycles the memory circuit through the selected access. The conventional asynchronous memory circuits have difficulty correctly restarting the self timing event in the middle of a cycle. Restarting the self timing event during an address transition timing space will not always produce consistent results. Holes in the address transition timing space commonly produce functional failures.